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Keerthi Sree

@keerthisree

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VLSI Physical Design Engineer skilled in 28nm PNR flows.

India

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What I'm looking for

I am seeking a role in VLSI physical design or related chip-design teams where I can apply PNR skills on modern nodes, continue learning EDA flows, contribute to timing closure, and grow within a collaborative engineering environment.

I am a motivated VLSI physical design engineer with hands-on experience in block-level implementation using Synopsys ICC2 and Fusion Compiler on 28nm technology. I have executed floorplanning, placement, CTS, routing and timing closure for a project with 40 macros and 52K instances, achieving signoff-quality implementation at 833MHz.

I work comfortably in Linux and Windows environments, know Verilog and Xilinx Vivado, and have a basic understanding of TCL scripting and timing closure techniques. I learn quickly, manage priorities effectively, and contribute proactively within cross-functional teams to improve QoR and meet delivery goals.

Experience

Work history, roles, and key accomplishments

Physical Design Engineer

Self Employed

Implemented block-level physical design for a 28nm chip using Synopsys Fusion Compiler and ICC2, completing floorplan, placement, CTS and routing for a design with 40 macros and 52K instances at 833MHz.

Synopsys ICC2 Clock Tree Synthesis Verilog Tcl