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Astitva Sharma

@astitvasharma

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VLSI engineer specializing in RTL design, verification, and FPGA/ASIC flows.

India

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What I'm looking for

I seek hands-on VLSI roles focused on RTL/verification or FPGA/ASIC implementation, with collaborative teams, opportunities for automation-driven verification and end-to-end design ownership.

I am a VLSI engineer with hands-on experience in RTL design, FPGA/ASIC implementation, and SystemVerilog/UVM verification, focused on delivering high-quality, synthesis-ready IPs and robust verification environments.

I have led and executed projects including a 4-way traffic light controller, a modular digital alarm clock, and an industry-standard 32-bit AHB-to-APB bridge with end-to-end RTL-to-GDS implementation and zero critical timing violations at 100MHz.

I prioritize automation, coverage-driven verification, and clear documentation—achieving resource-efficient synthesis, increased throughput, and faster debugging cycles—while actively advancing skills through certifications, internships, and conference research contributions.

Experience

Work history, roles, and key accomplishments

VLSI Design Engineer

Maven Silicon

Jun 2024 - Aug 2024 (2 months)

Executed full ASIC design and verification cycle for an AHB-to-APB bridge, contributing to 95% first-pass silicon success and reducing debug overhead via automated testbenches.

Verification ModelSim

Digital Design Engineer

Academic Projects

Engineered a 4-way intersection traffic controller in Verilog with a 12-state FSM, achieving 100% functional verification and a 25% improvement in traffic flow versus fixed-timing designs.

Verilog Quartus Prime

Project Lead

Academic Projects

Led design and verification of a modular digital alarm clock in Verilog, covering 20+ corner cases to ensure robust real-time operation and user interface via 7-segment drivers.

Verilog Verification Driver Logic

Education

Degrees, certifications, and relevant coursework

Vellore Institute of Technology

Bachelor of Technology, Electronics and Communication Engineering

2022 -

Grade: 8.12/10.0

Activities and societies: Projects: Traffic Light Controller, AHB to APB Bridge, Digital Alarm Clock; Internship at Maven Silicon; certifications in SystemVerilog/UVM and VLSI tool workshops.

Pursuing a BTech in Electronics and Communication Engineering with coursework and projects in RTL design, VLSI verification, and FPGA/ASIC flows; achieved CGPA 8.12/10.0.