Open to opportunities

Korrapolu Eswar Adithya

@korrapolueswaradithy

I’m an aspiring VLSI RTL design and verification engineer building ASIC/FPGA-ready modules, testbenches, and SVA-driven validation.

India

Message

What I'm looking for

I’m looking for a hands-on RTL design & verification role where I can build robust SystemVerilog/SVA testbenches, debug effectively, and validate designs on FPGA/ASIC flows with strong mentorship and real ownership.

I’m an aspiring VLSI Design and Verification Engineer focused on RTL design, functional verification, and FPGA prototyping. I’ve demonstrated this through a self-driven 100-design RTL repository spanning combinational, sequential, arithmetic, FSM, memory, and signal processing modules.

In my current Tejas VLSI Design Program, I’m building verification-ready RTL with SystemVerilog, SVA concurrent assertions, and coverage-focused testbenches. I designed a synchronous parameterised Dual-Port RAM and created a 15-file layered testbench (drivers, monitors, scoreboard, reference model) validated via simulation on EDA Playground.

Across internships, I’ve delivered end-to-end RTL work: architecting an AHB2APB Bridge with synthesizable Verilog and validating it with 100% functional coverage, and creating a custom 64x32-bit RAM IP that I linted, synthesized with timing constraints, and verified on Nexys-4 Artix-7 in Vivado. I also earned Global Rank 1 in the HDLBits Challenge (182 problems) and presented my CMOS sequence detector research at MNDCS (NIT Silchar).

Experience

Work history, roles, and key accomplishments

Current

VLSI Design & Verification Trainee

Current

Tejas VLSI Design Program

Nov 2025 - Present (7 months)

Designed a synchronous parameterised dual-port RAM in Verilog HDL with independent read/write ports and port-arbitration to prevent data corruption. Built a 15-file SystemVerilog testbench with drivers, monitors, scoreboard, reference model, SVA concurrent assertions, and functional covergroups; verified via EDA Playground.

Verilog SVA RTL Design Dual Port RAM EDA Playground

VLSI Design Intern

Sure Trust ProEd

May 2025 - Oct 2025 (5 months)

Engineered a custom 64x32-bit RAM IP in Verilog HDL, performing RTL linting, synthesis, timing constraints, and FPGA validation on Nexys-4 (Artix-7) using Vivado. Verified a vending machine controller using a 39-file layered SystemVerilog testbench with 4 protocol agents, per-interface checkers, reference model, and scoreboard; validated APB dispensing logic on EDA Playground.

Verilog Linting Synthesis Vivado APB Verification EDA Playground

RTL Design Intern

Maven Silicon Softech Pvt. Ltd.

Jun 2024 - Jul 2024 (1 month)

Architected a synthesizable AHB2APB Bridge in Verilog HDL with an AHB slave interface and APB FSM controller (IDLE–SETUP–ENABLE). Validated 8 single/burst read-write scenarios in ModelSIM with 100% functional coverage and achieved timing closure on Intel MAX V in Quartus Prime; verified RTL-to-gate equivalence via schematic review of 4 modules.

Verilog RTL Design ModelSim Quartus Prime Synthesis