At 3ST Technology, I designed and implemented an AMBA AHB interconnect in SystemVerilog, with three masters and four slaves. I also built a reusable UVM environment and verified single, burst, and concurrent transactions across 50+ test scenarios, achieving 95%+ functional coverage.
On the open-source Ibex RISC-V core, I integrated a 2-bit BHT branch predictor that improved prediction accuracy by approximately 18%. I also developed a predictor selector and performance monitoring unit, then verified the work with Verilator and C++ testbenches.
