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Twaheer N

@twaheern

Design Verification Engineer at Saksham Semiconductors who developed RTL for 5+ IP blocks and achieved 98% functional coverage with a UVM testbench.

India

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What I'm looking for

I'm looking for an entry-level Design Verification Engineer role focused on functional verification and coverage closure on semiconductor IP.

At Saksham Semiconductors, I developed synthesizable SystemVerilog RTL for digital IP blocks and verified designs against timing constraints in Xilinx Vivado. I also implemented Verilog-based RTL modules and checked their functional correctness through simulation.

With a three-person team at Saksham Semiconductors, I built a UVM testbench with agents, a sequencer, and a scoreboard for an ASIC IP block, achieving 98% functional code coverage. At Rooman Technology, I developed SystemVerilog/UVM testbenches for AMBA APB protocol verification and contributed to formal physical verification using Cadence Calibre.

I'm currently building a UVM RAL-based verification environment for a UART/I2C peripheral. I’m looking for an entry-level Design Verification Engineer role focused on functional verification and coverage closure on semiconductor IP.

Experience

Work history, roles, and key accomplishments

Digital Specialist

Saksham Semiconductors

Mar 2025 - May 2025 (2 months)

• Developed synthesizable RTL code for 5+ digital IP blocks using SystemVerilog, meeting design specifications and timing constraints verified in Xilinx Vivado.

• Designed and implemented Verilog-based RTL modules using Cadence Virtuoso and Xilinx Vivado, ensuring functional correctness across simulation runs.

• Collaborated with a team of three to build a complete UVM testbench (agents, sequenc

Analog Design Engineer

Saksham Semiconductors

Mar 2025 - May 2025 (2 months)

Learned the basics of analog circuit design including amplifiers and filters. Worked on creating and testing analog circuits using Cadence Virtuoso. Performed simulations like DC and AC analysis to check circuit performance. Gained hands-on experience with layout and checking tools like LVS and DRC.
Developed synthesizable RTL code for 5+ digital IP blocks in SystemVerilog, verified against timing

Design Engineering Intern

Rooman Technology

Oct 2024 - Feb 2025 (4 months)

• Developed SystemVerilog/UVM testbenches for AMBA APB protocol, enhancing test reusability.
• Conducted formal physical verification (LVS/DRC) using Cadence Calibre for SoC-level layout.
• Resolved violations pre-tape-out, ensuring design integrity and compliance.
• Contributed to Rooman Technology, a dynamic startup focused on innovative engineering solutions.