At NVIDIA, I design RTL and FPGA acceleration platforms for AI and high-performance computing workloads, improving FPGA processing throughput by 22%. I build Xilinx UltraScale+ prototypes, integrate AXI and memory interfaces, and use UVM verification to raise coverage from 85% to 98%.
Previously at Qualcomm, I developed reusable UVM environments and SystemVerilog verification components for ASIC and SoC subsystems. I automate large-scale regression, coverage, and debug workflows with Python, Perl, Tcl, and shell scripting while supporting tape-out readiness and first-pass silicon validation.
