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Bhanu Venkata Sai Gopi Ankala

@bhanuvenkatasaigopia

Design Verification Engineer at Bently Nevada, where I validate Orbit 60 platforms and automate regression testing.

At Bently Nevada (Baker Hughes), I develop and execute validation plans for board bring-up and verify Orbit 60 platforms through module integration and functional testing. I also automate regression testing and validation reporting in Python.

At FAMU-FSU College of Engineering, I implemented a PicoRV32 processor through the OpenLANE RTL-to-GDSII flow and developed a UVM verification environment. For my CH32V003-class RISC-V core project, I compared 520,452 instructions with zero mismatches, closed 330 of 330 coverage bins, and caught 12 of 12 injected bugs.

Experience

Work history, roles, and key accomplishments

Current

Electrical Design & Validation Engineer

Current

Bently Nevada (Baker Hughes)

Mar 2026 - Present (8 months)

Developed and executed validation plans for board bring-up, verifying power rails, sequencing, and clock/reset behavior. Reviewed board-level schematics and PCB layouts, and automated regression testing and report generation in Python.

Python Altium Oscilloscopes Waveform Analysis PCB Design Validation Test Planning Regression Automation

PCB Design Engineer

Micro1

Jun 2026 - Sep 2026 (3 months)

Verified PCB designs through DRC, connectivity checks, and layout inspection ahead of fabrication release. Investigated design defects through schematic review and simulation analysis.

PCB Design DRC Schematic Reviews Simulation Analysis

Research Assistant

FAMU-FSU College of Engineering

Feb 2024 - Dec 2025 (1 year 10 months)

Implemented a PicoRV32 RV32IMC processor in Verilog RTL through the OpenLANE RTL-to-GDSII flow on the SkyWater 130 nm PDK. Developed a UVM constrained-random verification environment and designed a signal conditioning circuit for thesis research.

Verilog RTL OpenLane SkyWater 130 PDK UVM Methodology SystemVerilog SPICE Python FPGA DRC LVS Static Timing Analysis

Hardware Design Engineer

Vlsi First

Jan 2022 - Nov 2023 (1 year 10 months)

Verified processor-based SoC subsystems in SystemVerilog/UVM testbenches using QuestaSim and ModelSim. Validated USB 3.0 and PCIe interfaces through protocol testing and link-training debug.

SystemVerilog UVM Methodology QuestaSim ModelSim USB 3.0 PCIe Debugging Python Regression Automation

Education

Degrees, certifications, and relevant coursework

micro1

PCB Design Engineer, PCB Design Engineer

Completed PCB Design Engineer certification from micro1 in May 2026.

Cadence

Digital Design and Verification, Digital Design and Verification

Completed Digital Design and Verification certification from Cadence.

Panimalar Institute of Technology

Bachelor of Engineering, Electronics and Communication Engineering

Grade: 3.7

B.E. in Electronics and Communication Engineering affiliated with Anna University, with a GPA of 3.7. Coursework includes VLSI Design, Computer Architecture and Organization, Microprocessors and Microcontrollers, and Embedded and Real Time Systems.

Cadence

Analog IC Design Implementation and Verification, Analog IC Design Implementation and Verification

Completed Analog IC Design Implementation and Verification certification from Cadence in February 2026.

Cadence

PCB Design, PCB Design

Completed PCB Design certification from Cadence.

Florida State University

Master of Science, Electrical and Electronics Engineering

Grade: 3.5

M.S. in Electrical and Electronics Engineering with a GPA of 3.5. Coursework includes Computer System Architecture, Advanced Microprocessor Systems, Advanced Digital Hardware, and Digital Integrated Circuit Design.