At Twinwing Labs Inc, I designed a low-latency FPGA tick-to-trade system that processes NASDAQ ITCH data and generates OUCH orders. The SystemVerilog design combines packet handling, an order book, trading strategies, and pre-trade risk checks.
I built its three-clock-domain architecture and packaged 14 blocks as Vivado IP-XACT IP. After synthesis and place-and-route, I fixed the worst timing paths with five pipelining changes that added no latency on the order path.
At Community Dreams Foundation, I served as Project Engineer for the Integrated Mini-SoC on VLSIVault, directing CPU microarchitecture from a single-cycle design to a five-stage pipeline. I also led eight RTL tracks and authored a Python assembler for firmware bring-up.
Earlier, at Aceic Design Technologies, I architected UVM verification for AMBA AXI4 Interconnect, SPI, and UART across more than 100 VIP components. My work helped achieve 99.8% coverage and 100% assertion closure across more than 2,000 tests.
