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Tony Chung

@tonychung

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Principal IC Layout Engineer at ams-OSRAM, leading sensor chip layout and debugging EM/IR issues with Voltus.

United States

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At ams-OSRAM, I work on sensor chip products as a Principal IC Layout Engineer, performing analog and mixed-signal layout based on TSMC 180nm. I create PEX, check block-level IR drop with RMAP, and use Voltus to investigate EM/IR errors.

I lead layout work across multiple sites, track schedules and progress, and prepare floorplan and tape-out status presentations. I also train new designers and mentor senior designers on leading blocks and projects.

At IC Enable, LLC, I performed analog and mixed-signal layout in TSMC FinFET technologies from 16nm through 5nm. I verified and debugged designs with Calibre, created PEX, and trained designers on FinFET process specifications.

At TEXAS INSTRUMENTS, INC., I worked on automotive power and sensor products, including layouts for regulators, converters, interfaces, and other custom circuits. Earlier, I worked on smart card chip products at EMOSYN and voice recognition chip products at INFORMATION STORAGE DEVICE, including full-custom layout and tape-out work.

Experience

Work history, roles, and key accomplishments

Current

Principal IC Layout Engineer

Current

ams-OSRAM

Mar 2022 - Present (4 years 8 months)

Leading analog and mixed-signal layout for sensor chip products on TSMC 180nm, coordinating multi-site teams and preparing tape-out documentation.

Virtuoso Calibre DRC LVS ERCs Ant DFM PEX RMAP Voltus Electromigration and IR Drop (EM IR)Project Management Mentorship

Senior Staff Analog Mask Designer

ams-OSRAM

Apr 2018 - Mar 2022 (3 years 11 months)

Performed analog and mixed-signal layout for sensor chip products, leading mask design teams across multiple countries and ensuring tape-out readiness.

Virtuoso Calibre DRC LVS ERCs Ant DFM PEX RMAP Voltus Electromigration and IR Drop (EM IR)Project Management Mentorship

Senior Analog Mask Designer

IC Enable, LLC

Mar 2014 - Apr 2018 (4 years 1 month)

Performed analog and mixed-signal FinFET layout in 16nm, 10nm, 7nm, and 5nm TSMC technologies, leading block-level designs and mentoring new designers.

FinFET TSMC 16nm 10nm 7nm Process 5nm Virtuoso Calibre DRC LVS ERCs Ant DFM PEX Voltus Electromigration and IR Drop (EM IR)Mentorship

Senior Analog Mask Designer

Texas Instruments, Inc.

Jan 2005 - Feb 2014 (9 years 1 month)

Led layout for automotive power and sensor chip products, including On-Star, air-bag, and braking systems, and performed full custom layout on various analog and mixed-signal blocks.

Virtuoso Assura TI K2 DRC LVS ERCs Ant DFM Signal Checker Arc DEF CMOS Bipolar BiCMOS DECMOS LDMOS Tape Out Mentorship

Senior Mask Designer

Emosyn

Jan 2001 - Jan 2005 (4 years)

In charge of layout for smart card chip products, including analog, NVM, SRAM, and digital sections, and responsible for tape-out procedures.

Virtuoso Calibre DRC LVS Ant Soft Checks Levels EEPROM OTPROM High Voltage Generators SRAM Tape Out

Analog Mask Designer

Information Storage Device

Jan 1999 - Jan 2001 (2 years)

Led layout team on voice recognition chip products, performing full custom analog and mixed-signal layouts on Winbond 0.5um process, and handled tape-out procedures.