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Saad Qureshi

@saadqureshi1

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Dedicated Electrical Engineer with over ten years of experience.

United States

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What I'm looking for

I am looking for a role that fosters innovation and collaboration, where I can lead projects and mentor junior engineers.

I am an Electrical Engineer with over ten years of experience in digital design engineering. My expertise encompasses project requirements, product development, design, verification, and lab validation. I hold a Master’s degree in Electrical Engineering from Johns Hopkins University, where I graduated with a GPA of 3.8/4.0. My academic background, combined with my professional experience, has equipped me with a strong foundation in both theoretical and practical aspects of electrical engineering.

Currently, I serve as a Senior Principal Digital Design Engineer at Northrop Grumman, where I lead technical efforts in developing requirements and project planning. I have successfully mentored a team of engineers, enhancing their understanding of design flow processes and configuration management. My role involves integrating complex components and troubleshooting designs, ensuring that projects meet stringent performance and reliability standards.

Throughout my career, I have worked with various organizations, including Raytheon and Annapolis Micro Systems, where I designed and integrated FPGA solutions. My technical skills include proficiency in tools such as Vivado, QuestaSim, and various programming languages, enabling me to tackle complex engineering challenges effectively.

Experience

Work history, roles, and key accomplishments

Current

Senior Principal Digital Design Engineer

Current

Northrop Grumman

Sep 2019 - Present (5 years 10 months)

Led the test load effort, managing requirements, planning, scheduling, and staffing while facilitating daily standups and weekly status meetings. Developed a JIRA plan for task tracking and mentored a team of engineers in design flow and configuration management.

Jira Agile Git Vivado QuestaSim Tcl Xilinx Zynq UltraScale+Partial Reconfiguration

Senior FPGA Design Engineer

Raytheon

Jan 2018 - Present (7 years 6 months)

Designed and integrated FPGA designs using Vivado 2017 tools, adding support for AXI4, Ethernet, and UART on Zynq 7045 SOC for RF transmitters. Utilized MentorGraphics QuestaSim for design and test benching FPGAs, employing ILA for testing and troubleshooting.

Vivado 2017 Ethernet UART Zynq 7045 SOC QuestaSim

Senior FPGA Design Engineer

Annapolis Micro Systems (AMS)

Jul 2016 - Present (9 years)

Designed and integrated Board Support Packages (BSP) for COTS boards with Xilinx UltraScale FPGAs using Vivado 2017 tools. Added support for HSS, PCIe, and LVDS on COTS boards and ADC/DAC DRFM mezzanine cards.

Xilinx UltraScale Vivado 2017 PCIe ADC DAC

FPGA Design Engineer II

Northrop Grumman

Jun 2015 - Present (10 years 1 month)

Designed and test-benched Microsemi FPGAs using QuestaSim, Synopsys, and Libero Design tools. Utilized logic analyzers and oscilloscopes for hardware testing and troubleshooting.

QuestaSim Libero Design Logic Analyzers Oscilloscopes

Electrical Engineer I

Raytheon

Jan 2013 - Present (12 years 6 months)

Involved in IFF (Identification Friend or Foe) products with an emphasis on firmware development. Designed and test-benched FPGAs using ModelSim, Synopsys, and Xilinx Design tools, employing ChipScope, logic analyzers, and oscilloscopes for testing and troubleshooting.

IFF Products Firmware ModelSim ChipScope Logic Analyzers Oscilloscopes

Education

Degrees, certifications, and relevant coursework

Johns Hopkins University

Master of Science, Electrical Engineering

2014 - 2016

Grade: 3.8/4.0

Completed a Master of Science degree in Electrical Engineering. Focused on advanced topics within the field, achieving a strong academic performance.

University of Florida

Bachelor of Science, Electrical Engineering

2008 - 2012

Grade: 3.48/4.0

Obtained a Bachelor of Science in Electrical Engineering. Gained foundational knowledge and practical skills in various electrical engineering principles.