At Arm, I execute CPU/SoC SystemVerilog and UVM test plans and regressions across configurations, tracking results toward verification signoff. I debug simulation failures with logs, SVA, RTL tracing, and waveforms.
I also maintain C-based verification tests, reproduce failures, and run targeted regressions for boot and control scenarios. I analyze functional and code coverage gaps and support closure through Linux, Git/Gerrit, and CI/pre-merge flows.
During my Design Verification internship at Cadence Design Systems, I focused on design verification and validation fundamentals, including SystemVerilog/UVM methodology and simulation workflows.
In my projects, I built UVM environments for AXI4-Lite and APB register verification, along with a Python regression pipeline. I also developed a human-reviewed tool that turns hardware/IP requirements into structured tests and candidate SVA concepts, with automated validation and GitHub Actions CI.
