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Aravind Pulugundla

@aravindpulugundla

Sr. Principal Architect Engineer at Palo Alto Networks, leading validation of NGFW Gen4–Gen6 SoCs and identifying four critical RTL defects.

United States

Message

At Palo Alto Networks, I lead ASIC validation architecture, silicon bring-up, and post-silicon validation for PANW NGFW Gen4, Gen5, and Gen6 SoCs. I identified and root-caused four critical RTL defects during silicon validation, contributing to silicon re-spin decisions and improved product quality.

I automated system-level performance validation using Python and Spirent TestCenter, and established Best Known Configuration processes across hardware, software, ASIC, and QA. I also led cross-functional debug across Broadcom Tomahawk3, Jericho2, and custom 400G ASIC subsystems.

At Broadcom Limited, I validated NetXtreme-E and BCM57xxx Ethernet controllers and NICs, including IEEE 802.3 compliance and UNH-IOL certification. Earlier, I designed FPGA solutions and prototypes at Sanmina SCI, Applied Micro Circuits Corporation (AMCC), LSI Logic Corporation, and Altera Corporation, including a 120G Interlaken FPGA prototype at LSI Logic Corporation.

Experience

Work history, roles, and key accomplishments

Current

Sr. Principal Architect Engineer

Current

Palo Alto Networks

Dec 2020 - Present (5 years 10 months)

Led ASIC validation architecture, strategy, and test planning for PANW NGFW Gen4, Gen5, and Gen6 SoCs. Automated system-level performance validation using Python and Spirent TestCenter, and led cross-functional debug across multiple subsystems.

ASIC Validation Silicon Bring Up Post Silicon Validation Ethernet Interlaken PCIe DDR4 HBM2e Python Spirent Test Center Root Cause Analysis Manufacturing Diagnostics AI Assisted Engineering

Master Engineer - Ethernet Controller R&D

Broadcom Limited

Dec 2014 - Oct 2020 (5 years 10 months)

Led hardware validation, silicon bring-up, and system debug of Broadcom NetXtreme-E and BCM57xxx Ethernet controllers. Developed IEEE 802.3 compliance validation and served as primary UNH-IOL liaison for plugfests and certification.

Hardware Validation Silicon Bring Up Systems Debugging Ethernet PCIe Serde IEEE 802.3 UNH IOL Signal Integrity EMI EMC ESD Testing

Principal Engineer - FPGA Design

Sanmina SCI

Mar 2014 - Dec 2014 (9 months)

Designed VHDL-based Microsemi FPGA solutions for Intel server motherboards, implementing power sequencing, serial communications, and platform health monitoring. Performed FPGA verification, hardware debug, and production-release qualification.

VHDL FPGA Microsemi Synplify Pro Libero Hardware Debug Integration Testing Production Releases

Principal Engineer - FPGA Design & Validation

Applied Micro Circuits Corporation (AMCC)

Aug 2012 - Mar 2014 (1 year 7 months)

Designed VHDL FPGA prototypes using Synopsys HAPS and Xilinx FPGAs to validate functional ASIC building blocks. Developed automated Python infrastructure for PVT characterization, reducing cycle time by more than 25%.

VHDL FPGA HAPS Xilinx ChipScope Python Serde PLL ADC DAC 10GBASE T 40G 100G Ethernet

Principal Engineer - ASIC Design & Validation

LSI Logic Corporation

Jul 2008 - Aug 2012 (4 years 1 month)

Provided technical leadership for 12 engineers executing design, validation, and lab bring-up of a 40nm networking ASIC. Led functional specification, validation architecture, and test plans for Fibre Channel and Ethernet PCS/MAC.

ASIC Design Validation Lab Bring Up Fiber Channel Ethernet Interlaken FPGA HAPS UNH IOL PLL Serde

Member of Technical Staff / FPGA Product Rollout Manager

Altera Corporation

Feb 2000 - Jul 2008 (8 years 5 months)

Led product-launch deliverables for 65nm Stratix III, Arria GX, and Cyclone FPGA families from first silicon through production deployment. Led a cross-functional team of 20 engineers and developed reference designs for Gigabit Ethernet, SRIO, and PCIe.