Any One

I built an AXI4-Lite slave with an 8-register memory-mapped bank, separate read and write FSMs, and a SystemVerilog testbench. I used constrained-random tests, assertions, and functional coverage to find and fix RTL bugs.

For an APB-to-SPI bridge, I implemented and verified protocol behavior, including timing, data integrity, and error handling. I also designed a synchronous FIFO and verified its boundary and back-to-back cases.

At Maven Silicon Softech Pvt. Ltd., I trained in front-end design and verification, including RTL coding, testbench development, constrained-random verification, assertions, and coverage using SystemVerilog and UVM. I enjoy RTL design and verification.

As an AI/ML Intern at Techshala Info Tech Solutions, I built a web interface that detects three types of brain tumor from uploaded MRI images using an ML model. At R&D Cell, Jain College of Engineering, I built a wirelessly controlled amphibious surface-cleaning robot with automatic waste segregation; the research paper was published by Springer.