GJGururaj Joshi
@gururajjoshi
Experienced VLSI physical design engineer specializing in RTL2GDS and low-power flows.
IndiaWhat I'm looking for
I am a VLSI physical design engineer with hands-on experience across RTL2GDS implementation, synthesis, placement & routing, and timing closure on advanced nodes including TSMC 22nm and 28nm.
I have developed low-power UPF flows for hierarchical designs, integrated isolation cells, level shifters and retention registers, and collaborated with DFT teams to validate MBIST and pattern simulations.
I led flow integration qualification and automation efforts, created regression frameworks for design-flow qualification, and owned Perforce data management integration with Cadence and Synopsys tools.
I mentor junior engineers, perform root-cause analysis for integration issues, and drive cross-functional teams to meet quality metrics and delivery timelines.
Experience
Work history, roles, and key accomplishments
RTL/Physical Design Engineer
Aranis
Developed SystemVerilog for CPU subblocks, performed linting and synthesis, and executed PNR flows to integrate and validate cpu_chip RTL into physical implementation. Supported design handoff and verification with Spyglass and synthesis toolflows.
Physical Design Engineer
UST Global
Led RTL-to-GDS implementation and synthesis/PNR for 22nm designs, achieving timing closure and sign-off while automating regression flows to improve qualification efficiency. Coordinated floorplanning, power planning and IP integrations for multiple chips and mentored junior engineers on PNR best practices.
Layout Engineer
Semtronics Microsystem
Performed block-level layout and floorplanning for ADC and analog library blocks on TSMC 90nm, managing differential-pair/current-mirror routing and ensuring matched DRC/LVS before GDSII streaming.
VLSI Design Intern
Infineon
Implemented Unified Power Format (UPF) for multi-voltage support, inserted level shifters/isolation cells and performed placement and layout verification for TSMC 90nm designs, ensuring DRC/LVS compliance for analog-critical routing.
Education
Degrees, certifications, and relevant coursework
MUManipal University
Master of Engineering, VLSI Design
2020 - 2022
Grade: 8.7 GPA
Completed ME in VLSI Design with a focus on low-power flows and physical design, graduating with an 8.7 GPA.
Sri Siddhartha Institute of Technology
Bachelor of Engineering, Electronics & Communication Engineering
Grade: 7.78 GPA
Completed BE in Electronics & Communication Engineering, graduating with a 7.78 GPA.
Tech stack
Software and tools used professionally
Availability
Location
IndiaAuthorized to work in
Job categories
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