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himanshu gomeHG
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himanshu gome

@himanshugome

Senior Physical Design Engineer specializing in advanced-node VLSI implementation.

India
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What I'm looking for

I want a hands-on physical design role at a technology-driven company, focused on advanced-node PnR, timing closure and sign-off, with collaborative teams and opportunities to solve complex congestion and manufacturability challenges.

I am a Senior Physical Design Engineer with extensive hands-on experience in floorplanning, placement, CTS, routing and sign-off at advanced process nodes including 3nm–28nm.

I have contributed to multiple successful PnR projects across clients such as Qualcomm, Nvidia (Mellanox), Intel and DNP, handling designs with up to ~4.5M standard cells and multi-million instance counts.

My work emphasizes congestion mitigation, timing closure, DRC/LVS/antenna/PAT sign-off readiness, UPF/VCLP issue resolution, and hotspot control using partial blockages, pin-placement strategies and path-grouping methods.

I seek roles where I can apply deep physical-design expertise on cutting-edge technologies and collaborate with cross-functional teams to deliver silicon that meets performance, power and manufacturability targets.

Experience

Work history, roles, and key accomplishments

TM
Current

Senior Physical Design Engineer

Tech Mahindra

Jul 2022 - Present (3 years 7 months)

Led block-level physical design (floorplanning, placement, CTS, routing, sign-off) across advanced nodes including 3nm–10nm, resolving timing, congestion and DRC/LVS/antenna issues to achieve sign-off-quality deliveries.

WI

Physical Design Engineer

Wipro

Oct 2020 - Jun 2022 (1 year 8 months)

Executed physical design tasks (placement, routing, CTS, ECO) for clients on nodes from 5nm to 28nm, addressing congestion, pin density and sign-off rule violations to meet project targets.

JT

Physical Design Engineer

Juntran Technologies

Aug 2018 - Feb 2020 (1 year 6 months)

Performed block-level P&R and sign-off activities for multiple clients (Qualcomm, Nvidia/Mellanox, Intel, DNP) across nodes including 3nm–28nm, mitigating congestion, hotspot and UPF/VCLP issues to achieve sign-off.

Education

Degrees, certifications, and relevant coursework

NC

National Institute of Electronics and Information Technology, Calicut

Postgraduate Diploma, Electronics and Communication

2016 - 2016

Grade: 71%

Completed a Postgraduate Diploma in Electronics and Communication with 71% from NIELIT Calicut.

GC

Government Ujjain Engineering College

Bachelor of Engineering, Electronic and Communication

2011 - 2015

Grade: 6.4 CGPA

Earned a Bachelor of Engineering in Electronic and Communication with a 6.4 CGPA.

MU

Model Higher Secondary School, Ujjain

Intermediate, Higher Secondary Education

Grade: 63%

Completed Intermediate (Higher Secondary) with 63% from Model Higher Secondary School, Ujjain.

Tech stack

Software and tools used professionally

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himanshu gome - Senior Physical Design Engineer - Tech Mahindra | Himalayas