Shagufta Mujeeb

I am a results-driven VLSI Physical Design Engineer with 3.3+ years of experience in RTL-to-GDSII flows and advanced-node (3nm/5nm) implementations. I focus on timing closure, power optimization, and delivering tapeout-ready designs using industry-standard tools.

My core expertise includes PnR with Cadence Innovus, PrimeTime-based STA and signoff, MCMM analysis, and low-power strategies such as power gating and multi-Vt. I consistently apply ECO techniques like buffer insertion, cell resizing, and clock skew adjustments to meet PPA targets.

I build automation and productivity tools using Tcl/Tk and Python — including a CBflow GUI and dashboards — and I promote best practices like version control (SVN) to reduce errors and speed up flows. I have experience validating designs for LVS, DRC, LEC, IRDrop, and power integrity.

I am passionate about continuous learning and innovation in VLSI methodologies, and I seek opportunities where I can contribute to high-performance ASIC design, mentor teams on CAD practices, and drive flow automation for faster, more reliable tapeouts.