nikhitha annthomas

I’m a detail-oriented VLSI Physical Design Engineer specializing in Place and Route (PnR), floorplanning, and clock tree synthesis, supporting full-chip implementation from RTL to GDSII. I’m currently employed at HCLTech and focus on robust timing closure and optimization for complex SoC designs.

In my work on 7 nm technology node SoC designs, I contribute to full-chip implementation and optimization, combining analytical problem-solving with disciplined sign-off readiness. I’ve worked extensively on PnR in the RTL to GDSII flow and used the RIDE flow for design implementation and validation.

I bring hands-on tool expertise with industry-standard Synopsys Fusion Compiler and Cadence Innovus, performing floorplanning, placement, clock tree synthesis (CTS), routing, and timing closure. I also support power integrity by assisting with PDN design and verification, along with power/performance/area best practices.

I’ve reinforced my physical design foundation through verification and sign-off workflows, including DRC/LVS, Setup and Hold Fixing, ECO implementation, and analyses such as EM and IR Drop. I’ve also participated in the “Kerala Reboot Design & Implementation: Hackathon” (Level 2) and completed training and internships that strengthened my scripting and programming confidence using TCL, Verilog, C, and MATLAB.