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Robin 11

@robin11

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Physical Design Engineer with 7 years’ experience optimizing timing, power, and layout across 2nm–14nm.

India

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What I'm looking for

I’m looking for a role where I can own physical design execution end-to-end—timing QoR, ECO/timing fixes, and low-power validation—using tools like Innovus/ICC2/PrimeTime, contributing across advanced nodes and critical blocks.

I’m a highly skilled Physical Design Engineer with 7 years of experience working on multiple partitions. My work spans floor planning, power planning, placement, clock tree synthesis, routing, timing analysis, ECO, and leakage recovery, including fixing design rule violations and closing timing up to 2.2Ghz.

I’ve used Fusion Compiler, ICC2, Innovus, and PrimeTime across 2nm/3nm, 4nm, 7nm, 10nm, and 14nm technologies. From block-level ORCA_TOP/MPW_GDDR6 to silicon testchips, I’ve driven timing QoR fixes, low power verification, formal verification, and post-synthesis constraints validation—while writing automation scripts in TCL, PERL, and Bash.

Experience

Work history, roles, and key accomplishments

Physical Design Engineer

Aritrak Technologies

Aug 2025 - Feb 2026 (6 months)

Executed physical-aware synthesis on six critical blocks for 2nm/3nm technologies and optimized performance and area. Performed timing QoR analysis with timing-violation fixes, then completed formal and low-power verification while validating timing constraints.

Physical Aware Synthesis Timing QoR Analysis Formal Verification Low Power Verification 2nm 3nm Physical Design

Physical Design Engineer

LeadSOC Technologies

May 2025 - Aug 2025 (3 months)

Implemented block-level physical design for ORCA_TOP on 32nm technology. Iterated over multiple floorplans and operating frequencies to evaluate physical implementation outcomes.

Multi Frequency Experimentation Clock Tree Synthesis Routing Eco 32nm Design

Physical Design Engineer

Insemi Technologies

Nov 2024 - Jan 2025 (2 months)

Successfully implemented physical design for the ORCA_TOP block in 32nm technology. Iterated floorplan architecture to improve power and area targets and evaluated design performance across various operating frequencies.

Multi Frequency Evaluation Routing 32nm ORCA_TOP

Lead Engineer

Synapse Techno Design Pvt. Ltd.

Sep 2020 - Sep 2023 (3 years)

Coordinated 4 blocks for a 4nm graphics processor and resolved floorplan-related issues to support implementation. Delivered physical design for AMD server MPU blocks (3 projects), handling placement, CTS, routing, PNR, ECO, timing closure, DRV fixes, DRC fixes, and RDL routing.

Floorplanning Issue Resolution Placements Clock Tree Synthesis Routing Base Metal ECO DRV Fixes DRC Fixes RDL Routing

Physical Design Engineer

Si2Chip Technologies Pvt. Ltd

Sep 2018 - Sep 2020 (2 years)

Implemented MPW_GDDR6 block in 7nm using Innovus, completing floorplan, placement of 1,835 ports and 1.4M instances, and performing CTS and routing with STA at 1.5GHz across 4 modes and 40 PVT corners plus ETM generation. Also supported a 45nm DMA_MAC dummy low-power implementation with PDmac1/PDmac2, addressing secondary PG, isolation, and level shifter insertion.

7nm Physical Design Large Scale Placement (1.4M Instances)PVT Corner Analysis ETM Generation Isolation Level Shifters

Physical Design Engineer

Bangalore Semiconductor Services

Aug 2017 - Jul 2018 (11 months)

Delivered 10nm Intel Ivy Creek testchip physical design (6 hard macros) including floorplan, placement, CTS, routing, and STA using ICC2 and PrimeTime. Addressed power discontinuity, macro timing arc issues, unclocked registers, diode connections, and executed ECO timing fixes, LEC and leakage recovery, and DRV fixes.

10nm Physical Design Clock Tree Synthesis Routing Timing ECOs Leakage Recovery (LEC)DRV Fixes DRC Fixes

Physical Design Engineer

Mindlance Technologies

Feb 2017 - Jul 2017 (5 months)

Completed 14nm Intel testchip implementation (XE_XBAR_WRAPPER) with 32 macros and ~250k instances, covering placement, CTS, and routing. Fixed timing violations, bound-placement issues, shorts, and unclocked registers using ICC and PrimeTime.

14nm Physical Design Placements Clock Tree Synthesis Routing Timing Violation Fixing Short Fixing Unclocked Register Fixes

Education

Degrees, certifications, and relevant coursework

Sathyabama University

Bachelor of Engineering (B.E.), Electrical and Electronics Engineering

Completed a B.E. in Electrical and Electronics at Sathyabama University in Chennai. Focused on fundamentals in electrical and electronics engineering.