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Mohit Patle

@mohitpatle

Senior Physical Design Engineer specializing in floorplan integration and reliability verification.

India
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What I'm looking for

I seek a challenging physical-design role at a high-quality engineering organization to apply floorplan, power-integrity and reliability expertise, collaborate cross-functionally, and lead RTL-to-GDS sign-off and release.

I am a Senior Physical Design Engineer focused on floorplan integration, power-grid design, MIM creation and reliability verification across advanced process nodes. I drive RTL-to-GDS sign-off, release activities and tapeout readiness with hands-on ownership.

I have led floorplan and power-plan efforts for advanced nodes (Intel 3, Intel 18A, TSMC 5nm/7nm/16nm), owning MIM creation, top-metal power grid refinement and EMIR flows to meet critical IR and capacitance requirements. I collaborate closely with RTL teams, block owners, CBB owners and PDN experts to resolve STA, extraction and PERC challenges under tight schedules.

My practical toolkit includes RedHawk, StarRC, ICC2, ICV, Calibre, STA and Synopsys flows, alongside DFT, synthesis and PNR experience. I seek technically challenging roles where I can apply my floorplan, power-integrity and reliability expertise to deliver silicon sign-off.

Experience

Work history, roles, and key accomplishments

IL
Current

Senior Physical Design Engineer

Intel Technologies India Pvt Ltd

Apr 2022 - Present (3 years 4 months)

Owned floorplan integration and reliability verification for advanced process nodes (Intel 3, 18A), delivering MIM and top-metal power grid solutions and leading RTL→GDS sign-off and release activities.

SL

Physical Design Engineer

Synopsys India Pvt Ltd

Jul 2018 - Apr 2022 (3 years 9 months)

Executed ASIC physical and electrical verification across multiple nodes, responsible for floorplan, power planning, MIM creation, PNR, STA, EMIR/PERC checks and sign-off activities.

Education

Degrees, certifications, and relevant coursework

National Institute of Technology, Tiruchirappalli logoNT

National Institute of Technology, Tiruchirappalli

Master of Technology

Grade: 8.32

Master of Technology completed in 2018 with CGPA 8.32.

Rajiv Gandhi Proudyogiki Vishwavidyalaya logoRV

Rajiv Gandhi Proudyogiki Vishwavidyalaya

Bachelor of Engineering

Grade: 7.1

Bachelor of Engineering completed in 2014 with CGPA 7.1.

JW

Jawahar Navodaya Vidyalaya, Waraseoni

All India Senior School Certificate Examination (AISSCE)

Grade: 81.2%

Completed All India Senior School Certificate Examination (AISSCE) in 2010 with 81.2% at Jawahar Navodaya Vidyalaya, Waraseoni.

JW

Jawahar Navodaya Vidyalaya, Waraseoni

All India Secondary School Examination (AISSE)

Grade: 79.2%

Completed All India Secondary School Examination (AISSE) in 2008 with 79.2% at Jawahar Navodaya Vidyalaya, Waraseoni.

Tech stack

Software and tools used professionally

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Mohit Patle - Senior Physical Design Engineer - Intel Technologies India Pvt Ltd | Himalayas