RVRishith Varma
@rishithvarma
ASIC Physical Design engineer skilled in block-level PnR, timing closure, and congestion resolution.
IndiaWhat I'm looking for
I am an ASIC Physical Design engineer trained at Semicon Technolabs with hands-on experience in block-level place-and-route (PnR) workflows, including synthesis, floorplanning, power planning, placement, CTS, and routing. I have delivered multi-node projects (32nm, 28nm) where I resolved timing, congestion, DRC, and power-grid issues using ICC2, Innovus, Genus and DC.
I focus on practical optimizations for timing closure and QOR — applying placement blockages, cell padding, path-group bounds, manual ECOs, and TCL scripting to automate fixes and reduce violations. I work comfortably in Windows and Linux environments and aim to contribute to teams needing reliable physical-design delivery and hands-on problem solving.
Experience
Work history, roles, and key accomplishments
ASIC Physical Design Engineer
Semicon Technolabs
Performed block-level place-and-route for multiple SoC blocks (32nm/28nm), resolving timing and congestion through floorplanning, placement blockages, cell padding and manual ECOs to achieve closure and clean DRCs.
Education
Degrees, certifications, and relevant coursework
Narayana Engineering College Gudur
Bachelor of Technology, Electronics and Communication Engineering
Grade: 8.3/10
Pursuing/Completed a Bachelor of Technology in Electronics and Communication Engineering with a CGPA of 8.3/10.
Narayana Junior College
Intermediate, Mathematics, Physics, Chemistry (MPC)
Grade: 9.1/10
Completed Intermediate (MPC) curriculum with a CGPA of 9.1/10.
Prospero English Medium High School
SSC, Secondary School
Grade: 8.5/10
Completed secondary school certificate with a CGPA of 8.5/10.
Availability
Location
IndiaAuthorized to work in
Job categories
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