At Google, I worked as a Design for Testability Trainee Engineer, updating the DFT specification and integrating a Staggered OCC design with Standard OCC RTL. I analyzed ATPG results across blocks, with pattern count and instantaneous power each 5% lower than Standard OCC, while CPU time was 15% higher.
I also designed and verified a temperature monitoring IP in SystemVerilog, then integrated it at block level and validated its synthesized netlist in Cadence Xcelium as ATPG GLS; all patterns passed. In my projects, I designed Verilog hardware including a ray tracer datapath, a FIFO and SPI data-exchange system, and a single-cycle processor with cache management.
