At HCLTech, I build and maintain DFT-in-RTL automation for ASIC DFT and ATPG workflows, supporting DFT specification, environment generation, flow configuration, and validation for a Renesas Electronics client. I work with DFT, design, and validation teams on flow requirements, debugging, and production issues.
I developed a Python regression orchestration tool that reduced execution time for 10 DV regression batches from about 100 hours sequentially to 10.5–11 hours in parallel. I also built an assertion log analyzer that compares results across simulation logs and a SystemVerilog test-library generator for creating test collateral.
On my HydroGuard project, I built an underwater ROV for marine structure inspection and integrated real-time crack detection, with the work published at IEEE ICTEST 2025 and Springer ICSMS 2026. I also developed a solar-powered water-monitoring system with ESP32 devices, a safety-focused pump controller, and a FastAPI dashboard.
