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Shwetha Patil

@shwethapatil1

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DFT / VLSI Design Engineer at Insemi Technologies, executing ATPG flows and SCAN insertion for ASIC design.

India

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At Insemi Technologies Pvt Ltd, I perform SpyGlass and DRC checks, execute ATPG flows and simulations, and resolve timing issues while supporting SSN project delivery.

Earlier at Insemi Technologies Pvt Ltd, I developed ATPG patterns, performed SCAN insertion, and debugged coverage gaps. I also worked as an Assistant Professor at MVJ College of Engineering.

Experience

Work history, roles, and key accomplishments

Current

Senior Design Engineer

Current

Insemi Technologies Pvt Ltd

Jan 2026 - Present (9 months)

Performed SpyGlass and DRC checks reducing design violations. Executed ATPG flows and simulations improving fault coverage, and resolved timing issues while supporting SSN project delivery.

Spyglass DRC SCAN ATPG Static Timing Analysis SSN

Design Engineer

Insemi Technologies Pvt Ltd

Jan 2025 - Jan 2026 (1 year)

Developed ATPG patterns and improved SCAN coverage. Performed SCAN insertion and debugged coverage gaps.

SCAN ATPG Scan Insertion Coverage Analysis

Associate Design Engineer

Insemi Technologies Pvt Ltd

Oct 2023 - Jan 2025 (1 year 3 months)

Built strong foundation in ASIC design flow and DFT. Worked in team environment to support design cycles, and executed SCAN insertion and ATPG generation.

ASIC Design DFT Scan Insertion SCAN ATPG