varchasv t26

I’m a DFT Engineer with ~4 years of experience in scan insertion, ATPG, and Varchasv memory DFT for large scale SoCs. I specialize in lowering pattern count and test coverage optimization, with hands-on ownership across unit level synthesis, scan insertion, and ATPG verification of memory arrays.

As an ArrayDFT Team Lead, I lead the DFT architecture for alternative SRAM verification using ATPG languages for both Stuck-at and FTM, including RTL implementation and SRAM library model translation for RAM-Seq ATPG. I’ve deployed RAM-Seq ATPG tests for full chip SoCs, and translated the complete methodology flow from in-house Scan and Synopsys TMAX to Siemens Tessent based Scan and ATPG.

I work closely with Timing, Physical design, and Place n Route teams to meet DFT requirements, and I handle official sign-offs on initialization sequence of JTAG regs for memory wrappers. My background also includes a Product Validation Internship at Cadence where I synthesized large scale DFT inserted netlists using Genus DFT Solution and performed fault testing with MODUS ATPG.