SAPTAK MAITY

SM

Looking for a job

SAPTAK MAITY

@saptakmaity

VLSI Design Engineer working on an FPGA FFT denoising accelerator, with RTL-to-GDS and low-power ASIC design experience.

On my OTS-LW-FFT project, I optimized a pipelined FPGA denoising architecture with a 9-DSP Karatsuba scheme, closing timing at 50.68 MHz. I also verified its functional and performance characteristics across a 12-image benchmark suite.

For an asynchronous FIFO project, I designed and implemented a CDC-aware multi-clock RTL design and completed its Sky130 RTL-to-GDS flow, achieving timing closure with zero DRC/LVS violations. I’ve also implemented a low-power divider using clock gating and RTL refactoring, and designed a low-power domino address decoder.

Experience

Work history, roles, and key accomplishments

EC

Network Security Trainee

Engineers Study Centre

Oct 2022 - Nov 2022 (1 month)

Completed practical training on network infrastructure security, protocol analysis, and threat detection fundamentals.

Network Security Protocol Analysis Threat Detection

Education

Degrees, certifications, and relevant coursework

JU

Jadavpur University

M.Tech., Microelectronics & VLSI Design

Grade: 7.81/10

Pursuing M.Tech. in Microelectronics & VLSI Design with a GPA of 7.81/10, expected to complete in May 2027.

NG

NSEC, Garia

B.Tech., Electronics & Communication Engineering

Grade: 8.78/10

Completed B.Tech. in Electronics & Communication Engineering with a CGPA of 8.78/10.

KH

K.T.P.P. High School (H.S.)

Higher Secondary, General

Grade: 78.60%

Completed Higher Secondary education with a percentage of 78.60%.

KH

K.T.P.P. High School (H.S.)

Secondary, General

Grade: 91.71%

Completed Secondary education with a percentage of 91.71%.

Tech stack

Software and tools used professionally

Perl

MATLAB

Verilog

Availability

Looking for a job

Location

India

Authorized to work in

Salary expectations

70k+ INR

Social media

Job categories

VLSI Engineer Fpga Engineer ASIC Design Engineer Physical Design Engineer

Skills

RTL Design RTL To GDS FPGA Design ASIC Design Physical Design Static Timing Analysis Logic Synthesis Low Power Design Clock Tree Synthesis Place And Route Design For Test Verification Clock Domain Crossings Power Performance Area Optimization Verilog

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