At Google, I worked as a Design for Testability Trainee Engineer, updating the DFT specification for Staggered OCC and integrating it into Standard OCC's RTL design. I also wrote a TCL script to update the ATPG setup.
I analyzed ATPG across blocks, comparing pattern count and instantaneous power with Standard OCC, and executed the ASIC design flow from front-end DFT through back-end ATPG.
I designed and verified a temperature-monitoring IP in SystemVerilog using a Mealy FSM and pattern counter. I validated hard-macro test cases in QuestaSim and integrated the IP at block level, where all patterns passed ATPG GLS validation.
In my projects, I designed Verilog hardware including a ray tracer datapath, FIFO and SPI data exchange, and a single-cycle processor with cache management. I also designed a transistor-level multiplexer and simulated its layout using Microwind 3 and Cadence Virtuoso.
