Interested in VLSI physical design and have hands-on experience with VLSI concepts and tools like Design Compiler (DC) and IC Compiler II (ICC2). Done projects related to the physical design flow, focusing mainly on backend tasks like floorplanning, power planning, CTS, and routing. Reduced violations such as DRC and LVS, and timing violations by reducing setup and hold slack.
TS
Looking for a job
Tejomurthula Karthikeya Sarma
@tejomurthulakarthike
Graduate in Electronics and Communication Engineering at Raghu Institute Of Technology. Interested in VLSI Physical Design and concepts of it.
IndiaExperience
Work history, roles, and key accomplishments
ST
VLSI Physical Design Trainee
Sumedha Institute of Technology
Nov 2024 - Jun 2025 (7 months)
Trained in RTL-to-GDSII physical design flow using Synopsys Design Compiler and IC Compiler II. Gained hands-on exposure to synthesis, floorplanning, power planning, placement, CTS, routing, STA, timing closure, and DRC/LVS analysis on 28nm technology.
BT
Python Intern
BIST Technologies
Feb 2024 - Apr 2024 (2 months)
Completed a Python internship at BIST Technologies.
AR
Industrial Trainee
All India Radio
Jun 2023 - Jul 2023 (1 month)
Completed an industrial training at All India Radio.
TC
Completed a technical internship at TCS.
Education
Degrees, certifications, and relevant coursework
RT
Raghu Institute of Technology
Bachelor of Technology, Electronics and Communication Engineering
2020 - 2024
Grade: 7.48/10
Pursued Bachelor of Technology in Electronics and Communication Engineering with a CGPA of 7.48/10.
NC
Narayana Junior College
Intermediate, Intermediate
2018 - 2020
Grade: 9.16/10
Completed Intermediate education with a CGPA of 9.16/10.
NP
NPTEL
VLSI Physical Design – NPTEL Certificate, VLSI Physical Design
Earned a certificate in VLSI Physical Design.
Availability
Looking for a job
Location
IndiaAuthorized to work in
Salary expectations
300k-400k INR
Social media
Job categories
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