JAHNAVI MUDILI

I'm pursuing a B.Tech in Electronics and Communication Engineering at the Institute of Aeronautical Engineering, with hands-on VLSI design work using Synopsys Design Compiler and IC Compiler II.

I've completed RTL-to-gate-level netlist conversion projects at 28nm, resolving check timing and check design issues for blocks operating at up to 1000MHz. I also fixed timing violations across multi-clock designs using optimization techniques without affecting other paths.

In a block-level physical design project, I floorplanned and placed a 107,442-leaf-cell block with 33 macros, optimizing macro placement to reduce congestion and improve routing.

During my internship at Bharat Heavy Electricals Limited, I gained exposure to industrial manufacturing and power plant equipment maintenance, assisting with inspection and analysis of turbines, boilers, and heavy electrical machinery.