Sailex Salam

SS

Looking for a job

Sailex Salam

@sailexsalam

VLSI physical design engineer focused on Cadence Innovus RTL-to-GDSII projects, including a 211,492-cell RISC-V processor with clean signoff.

I completed two RTL-to-GDSII physical design projects in Cadence tools, including a 70,824-cell neural network design and a 211,492-cell RISC-V processor with a SiLU extension. Both projects achieved clean DRC and LVS signoff.

For the neural network ASIC, I implemented floorplanning and PDN design, placement, clock tree synthesis, and routing. I also fixed hold violations through ECO delay-buffer insertion and Tempus optimization, and analyzed static IR drop.

As a Teaching Assistant (Peer Mentor) — VLSI Design at Visvesvaraya National Institute of Technology, I mentored M.Tech students in Verilog RTL and the RTL-to-GDSII flow. I also authored lab exercises and assignments covering synthesis, physical design, and STA signoff.

Experience

Work history, roles, and key accomplishments

VT

Teaching Assistant (Peer Mentor)

Visvesvaraya National Institute of Technology

Jan 2025 - Dec 2026 (1 year 11 months)

Mentored first-year M.Tech students in Verilog RTL design and the complete RTL-to-GDSII ASIC flow using Cadence Genus, Innovus, and Tempus through 4 hours of weekly lab sessions. Designed and authored lab exercises, assignments, and grading rubrics covering logic synthesis, floorplanning, CTS, place-and-route, and STA signoff methodology.

Verilog RTL To GDSII Genus Cadence Innovus Cadence Tempus Logic Synthesis Floor Planning CTS Place And Route STA

Education

Degrees, certifications, and relevant coursework

VT

Visvesvaraya National Institute of Technology

M.Tech, VLSI Design

2024 -

Grade: 8.81

Pursuing M.Tech in VLSI Design with a CGPA of 8.81.

MU

Manipur Technical University

B.Tech, Electronics and Communication Engineering

2020 - 2024

Grade: 7.55

Completed B.Tech in Electronics and Communication Engineering with a CGPA of 7.55.

UD

Udemy

Complete ASIC Design Flow: VLSI from Idea to Silicon, VLSI Design

Completed a certification in Complete ASIC Design Flow: VLSI from Idea to Silicon.

UD

Udemy

ASIC Design Verification using SystemVerilog, ASIC Design Verification

Completed a certification in ASIC Design Verification using SystemVerilog.

CO

Coursera

Neural Networks and Deep Learning, Deep Learning

Completed a certification in Neural Networks and Deep Learning.

Tech stack

Software and tools used professionally

Python

Linux

Shell

Availability

Looking for a job

Location

India

Authorized to work in

Portfolio

github.com/Sailex-Salam/Semi-Custom-ASIC-implementation-of-Neural-Network--AI-inferencing--in-hardware

Salary expectations

70k+ INR

Social media

Job categories

Physical Design Engineer ASIC Design Engineer VLSI Engineer

Skills

Physical Design RTL To GDSII Floor Planning Power Planning Placements Clock Tree Synthesis Routing Static Timing Analysis Timing Closure Eco DRC LVS ERCs Antenna Check IR Drop Analysis

Interested in hiring Sailex?

You can contact Sailex and 90k+ other talented remote workers on Himalayas.

People also viewed

View all talent

Get matched with your dream remote job

Sign up now and join over 250,000+ remote workers who receive personalized job alerts, curated job matches, and more for free!