At RV-SKILLS Center For Emerging Technologies, I executed a full ASIC block-level physical design implementation in 40nm technology using Synopsys ICC2. The design included four clocks, nine power domains, 34 macros, and 0.4M standard cells.
I handled floorplanning, power planning, placement, clock tree synthesis, routing, and physical signoff. I optimized the power mesh through IR-drop analysis and resolved routing shorts and antenna violations to achieve a DRC-clean routed netlist.
During the project at RV-VLSI Design Center, I completed the ASIC physical design flow and addressed setup and hold timing violations during timing closure. I also refined placement constraints to manage congestion in high-utilization regions.
For my Accident Detection and Report System project at PVG’s College of Engineering and Technology, I developed an IoT-based system using an ATmega328P, accelerometer, and GPS sensors. I implemented the firmware in Embedded C for collision detection and GPS-based location reporting.
