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SADU NITEESH

@saduniteesh

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I'm a VLSI physical design engineer focused on RTL-to-GDSII implementation, timing analysis, and block-level PnR.

India

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What I'm looking for

I'm looking for an opportunity in VLSI physical design where I can apply RTL-to-GDSII, block-level PnR, timing analysis, and Synopsys IC Compiler skills while continuously learning and growing.

I've completed six months of professional VLSI physical design training through DDU-GKY and the Government of Andhra Pradesh, with hands-on exposure to Synopsys IC Compiler 1.

I worked on ORCA_TOP physical design projects at 32nm and 28nm, handling floorplanning, power planning, placement, CTS optimization, routing, and timing-path analysis. I manually placed macros using fly-line analysis, addressed congestion, and analyzed violations across placement, CTS, and routing stages.

I bring an Electronics and Communication Engineering background and a practical understanding of RTL-to-GDSII design implementation, digital electronics, CMOS, ASIC flows, and synthesis flows.

I've also designed an I2C bus protocol using Verilog, including a single-master I2C module and testbench simulated in Xilinx ISE.

Experience

Work history, roles, and key accomplishments

VLSI Physical Design Trainee

DDU-GKY

Completed 6 months professional training in VLSI physical design domain under DDU-GKY and government of Andhra Pradesh. Gained practical exposure on Synopsys IC Compiler and block-level implementation concepts.

VLSI Power Planning CTS Routing Tcl Linux