Sreemoyee Saha

I’m a hardware-focused professional with hands-on experience in UVM verification and protocol design, currently advancing my skills through VLSI Design and Verification training at CDAC ACTS Pune. I also bring real-world evaluation experience as an LLM Quality Analyst, where I validate mathematical reasoning and review technical datasets for correctness and consistency.

In my RTL projects, I designed and verified an AXI4-Lite to APB protocol bridge, including an APB master interface, an FSM-based controller, and a full UVM environment with driver, monitor, scoreboard, and constrained-random sequences. I also built an asynchronous FIFO in Verilog with Gray code synchronization, metastability mitigation via two flip-flop synchronizers, and simulation validation using Vivado and waveform analysis.

Beyond digital design, my MSc thesis work deepened my analytical fundamentals through RF characterization of RF-sputtered HfO MOS capacitors using C–V, G–V, and J–V measurements, including investigation of leakage mechanisms and dielectric reliability before and after annealing. I’m motivated by engineering work that prioritizes correctness, validation, and reliable behavior across edge cases.