Mamkar Regonda

I am a VLSI back-end engineer with hands-on experience delivering mixed-signal ASIC tape-outs at the 180nm process node. I led digital backend flows from RTL synthesis through GDSII, collaborating closely with analog teams for seamless integration.

At my current role I achieved a 95% timing closure rate, reduced setup violations by 80%, and implemented Genus synthesis script optimizations that improved area and delay by 15%. I executed over 50 Innovus PnR runs with incremental ECOs and clock-tree synthesis to meet timing goals.

I architected and implemented multiple Verilog HDL blocks for a gyroscope ROIC, achieved 100% functional verification with Xcelium, and delivered first-pass-silicon results with zero DRC/LVS violations. My workflow emphasizes reproducible documentation, version control, and cross-functional coordination.

I am committed to continual learning and practical application of EDA tools and methodologies, and I bring a combination of technical rigor, hands-on tape-out experience, and leadership from student initiatives to each project I join.