At Yes 2 You, I developed learning materials introducing digital logic, basic electronics, and VHDL. I also maintained and troubleshot the front-end web platform.
As a Graduate Teaching Assistant for Purdue University's EPICS Program, I mentored engineering teams as they debugged digital circuits, FPGA logic, and embedded systems. I provided feedback on schematics and simulation results and assisted with validation and troubleshooting.
At L&T, I tested the Intelligent Motor Management Relay (iMMR), including relay trip timing and fault response, and documented the results in a schematic-based technical report.
In my projects, I implemented an 8-bit Manchester adder using custom CMOS layout and developed a transistor-level 8×8 Dadda multiplier. I also designed a VHDL morphological image-processing system for PYNQ-Z2, using a 3×3 sliding-window architecture and AXI-DMA.
