At AMD India, I work on block-level physical design implementation from netlist to GDSII for 6 nm ASIC designs. I've contributed to five tape-outs across floorplanning, placement, clock tree synthesis, routing, and physical verification.
In block-level design planning, I performed macro and TSV placement and implemented multi-voltage power grids, including custom structures for analog macros. I also addressed congestion with instance padding and blockages.
I delivered placement, CTS, and routing for timing closure, and worked on signal-integrity fixes, ECOs, and DRC, LVS, and ERC checks. For outgoing clocks, I created a custom clock-building approach that reduced latency by 55% to meet top-level targets.
On full-chip work, I implemented logical ECOs and handled deliverables for a 20-block design, including LVS, DRC, and antenna analysis. I also developed Tcl and Python scripts for clock-tree building, DRC fixes, and timing-data presentation.
