20 Janhavi Saraf
@20janhavisaraf
I design Verilog-based digital ICs, processors, ASIC flows, and embedded hardware systems.
IndiaWhat I'm looking for
I've designed Verilog-based digital systems including an 8-bit ALU taken from RTL to GDSII, a 32-bit five-stage pipelined RISC-style processor, and an AXI4-Lite PWM peripheral on PYNQ-Z2.
During my Semiconductor Laboratory internship, I designed a bootloader with UART, MMIO, SPI, and I2C interfaces and worked on a 6T SRAM cell array in Cadence Virtuoso. I also used MATLAB/Simulink sensor fusion to improve simulated 5G NR positioning accuracy from 102.9 m to 0.41 m.
Experience
Work history, roles, and key accomplishments
Intern – Semiconductor Laboratory
Ministry of Electronics
Jul 2026 - Aug 2026 (1 month)
Designed a bootloader with UART receiver, MMIO interface, and SPI/I2C protocols in Verilog, integrating with core and program memory. Also designed a 6T SRAM cell array in Cadence Virtuoso.
5G Technology Training Program
COEP
Jun 2025 - Jul 2025 (1 month)
Authored a conference paper analyzing positioning accuracy improvements using sensor fusion.
Education
Degrees, certifications, and relevant coursework
MIT World Peace University
Bachelor of Technology, Electronics and Telecommunication Engineering
2023 -
Grade: 9.05/10
Pursuing a B.Tech in Electronics and Telecommunication Engineering with a CGPA of 9.05/10.
Tech stack
Software and tools used professionally
Availability
Location
IndiaAuthorized to work in
Salary expectations
Job categories
Interested in hiring 20 Janhavi?
You can contact 20 Janhavi and 90k+ other talented remote workers on Himalayas.
Message 20 JanhaviGet matched with your dream remote job
Sign up now and join over 250,000+ remote workers who receive personalized job alerts, curated job matches, and more for free!
