Roopesh KOTA

At NG RAN, IIT Hyderabad, I designed and verified RTL modules for AXI4-Stream architectures, improving data throughput by 25% through pipelined datapath optimization. I also developed FIFO and skid-buffer modules that reduced data loss under backpressure by 40%.

I simulated and debugged RTL in QuestaSim and synthesized designs in Xilinx Vivado, resolving functional bugs across five modules. I also built testbench components for antenna data validation, raising functional coverage from 60% to 90%.

In personal projects, I developed RTL and SystemVerilog testbenches for AXI, AHB, APB, and UART. I also built a SystemVerilog/UVM verification environment for an AHB-to-APB bridge, using testcases, assertions, and functional coverage to verify protocol compliance.