I've designed CMOS gates in Cadence Virtuoso, built and validated an FPGA traffic-light controller, and am fabricating an MTJ-based in-memory logic array for future SoC deployment. During my internship at Bharat Electronics Limited, I mapped Xilinx Zynq SoC defense communication architectures and audited PCB and EMI/EMC qualification processes.
On the software side, I built a FastAPI and Leaflet landslide-risk decision-support system using a Mixture-of-Experts model, accepted for presentation at IN-GARSS 2026. I've also delivered a CUDA-parallel convolution kernel with a 59x speedup over NumPy and deployed an interactive ML spam classifier.
