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Valsa Shiva

@valsashiva

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RTL design engineer building Verilog/SystemVerilog modules and a 5-stage RISC-V processor for FPGA.

India

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Through my 100 Days of RTL Design self-directed program, I designed and verified more than 30 digital modules, including controllers, pipelined architectures, and UART/SPI interfaces, using ModelSim and Vivado.

I designed a modular 5-stage RV32I RISC-V processor with Physical Memory Protection, then verified its functionality with simulation testbenches. I also implemented the RTL-to-bitstream flow and debugged the design on an Artix-7 FPGA.

For my FPGA I2C GPIO Expander project, I implemented a 16-bit I2C slave with a configurable register map and interrupt logic. I validated it in ModelSim and deployed it on a Basys 3 FPGA.

I also designed a 2-layer USB-to-I2C PCB interface and a 2×2 Wallace Tree multiplier using Transmission Gate logic. My work includes PCB design checks and signal-integrity simulation, as well as SPICE analysis of power and delay.

Experience

Work history, roles, and key accomplishments

100 Days of RTL Design

Self-Directed Program

Jan 2025 - Present (1 year 9 months)

Undertook a self-driven challenge focused on mastering Verilog/SystemVerilog RTL design, covering FSMs, datapath design, communication protocols, and timing analysis. Designed and verified 30+ digital modules including controllers, pipelined architectures, UART/SPI interfaces, and embedded communication systems using ModelSim and Vivado.