Open to opportunities

ANISH MONDAL

@anishmondal

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VLSI design and verification engineer skilled in RTL and system verification.

India

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What I'm looking for

I seek VLSI/RTL roles focused on design and verification with opportunities for hands-on FPGA/ASIC work, mentorship, and growth in low-power and verification-driven design.

I am a VLSI design and verification engineer with hands-on experience in Verilog, SystemVerilog, UVM, assertions, coverage-driven verification and shell scripting, currently working as an Assistant Engineer in VLSI Design. I hold an M.Tech in Functional Material and Devices from IIT Kharagpur and have completed projects on image compression using DWT with a 16-bit Dadda multiplier and an energy-efficient approximate multiplier (CAAM) that improved PDP by up to 39.9%.

I have implemented an Asynchronous FIFO with a SystemVerilog testbench, designed a RISC-V single-cycle processor verified on FPGA toolchains, and completed coursework and training in Digital IC Design, STA, CMOS design and verification flows. I bring practical tool experience (ModelSim, Vivado, Quartus, EDA Playground), familiarity with communication protocols (SPI, I2C, UART, AHB/APB/AXI), and a commitment to robust verification and low-power digital design.

Experience

Work history, roles, and key accomplishments

Current

Assistant Engineer VLSI

Current

Silicon Interfaces

Oct 2023 - Present (2 years)

Developed and verified RTL using Verilog/SystemVerilog and UVM, implemented assertions and coverage metrics, and automated verification flows with shell scripting to improve verification efficiency.

Verilog Coverage Shell Scripting ModelSim

M.Tech Researcher

Indian Institute of Technology Kharagpur

Jan 2023 - Apr 2025 (2 years 3 months)

Led M.Tech projects on image compression (DWT with 16-bit Dadda multiplier) achieving up to 32:1 compression and developed an 8-bit compressor-based adaptive approximate multiplier improving PDP and power efficiency by up to 39.9%.

Digital Signal Processing Matlab ModelSim Dadda Multiplier

Education

Degrees, certifications, and relevant coursework

Indian Institute of Technology Kharagpur

Master of Technology, Functional Material and Devices (Solid State Devices)

2023 - 2025

Grade: 8.09

Activities and societies: M.Tech projects: Image Compression using DWT with Dadda Multiplier; CAAM: Compressor-Based Adaptive Approximate Multiplier; TA for B.Tech Physics Lab.

M.Tech in Functional Material and Devices (Solid State Devices) with coursework and projects in VLSI, image compression, and approximate multipliers; graduated with a CGPA of 8.09.

Institute of Engineering and Management

Bachelor of Technology, Electrical Engineering

2017 - 2021

Grade: 7.36

Activities and societies: Projects: Asynchronous FIFO (Verilog/SystemVerilog), RISC-V single-cycle processor design, various mini projects using Xilinx Vivado.

Bachelor of Technology in Electrical Engineering with coursework in digital and analog electronics, VLSI design flow, and semiconductor device physics; graduated with a CGPA of 7.36.