Open to opportunities

Prajyot Patil

@prajyotpatil

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Electronics engineer specializing in VLSI design, verification, and CADENCE workflows.

India

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What I'm looking for

I seek a hands-on VLSI/verification role at an innovative semiconductor team, with mentorship, clear growth paths, and collaborative culture.

I am an enthusiastic Electronics Engineer focused on VLSI design, verification, and CADENCE tool flows. I combine hands-on experience in digital and analog VLSI with practical knowledge of functional simulation and SoC architecture.

During multiple internships I worked on SystemVerilog-based digital design and verification, developed testbenches, and designed an AHB2APB bridge with functional simulation. I have also performed CMOS layout design and post-layout checks (DRC/LVS) using CADENCE Virtuoso.

I am passionate about semiconductor innovations and enjoy teaching and mentoring — I led a short boot camp session on digital VLSI for junior students and received a letter of appreciation. My academic record includes a strong CGPA and national-level awards and scholarships.

I seek to contribute to cutting-edge chip design projects where I can apply my verification and layout skills, learn advanced SoC methodologies, and grow within collaborative engineering teams.

Experience

Work history, roles, and key accomplishments

Engineering Intern

KarMic Design Pvt. Ltd.

Mar 2025 - Jun 2025 (3 months)

Gained hands-on experience in digital design and verification using SystemVerilog, contributing to testbench development and functional simulation workflows during a short-term internship.

Digital Design Verification)TestBench Development

Digital VLSI Trainer

Boot Camp

Apr 2025 - Apr 2025 (0 months)

Taught junior students fundamentals of digital VLSI, improving their practical understanding of Verilog and basic digital design concepts during a short instructor engagement.

VLSI Verilog Teaching Curriculum Development

Engineering Intern

Rooman Technologies Pvt. Ltd.

Sep 2024 - Feb 2025 (5 months)

Worked on digital design and verification using SystemVerilog, contributing to simulation and verification tasks across projects from Sept 2024 to Feb 2025.

Digital Design Verification)TestBench Development

Engineering Intern

NI LabVIEW & CADENCE Tool

Jan 2024 - Feb 2024 (1 month)

Developed CMOS inverter, NAND, and NOR layouts in Cadence Virtuoso, performed DRC/LVS checks and conducted post-layout simulations to validate circuit behavior.

LVS Analog Circuits

Virtual Intern

Salesforce Trailblazers

Aug 2023 - Oct 2023 (2 months)

Completed a virtual program covering cloud computing and CRM fundamentals, gaining exposure to Salesforce platform concepts and cloud-based workflows.

Cloud Computing CRM Virtual Collaboration

Engineering Intern

Maven Silicon

Designed and verified an AHB-to-APB bridge, developed testbenches and performed functional simulation while contributing to SoC architecture and design verification activities.

Verification)TestBench Development