Pavan Kumar B

I'm targeting Digital Design Engineer roles, bringing hands-on RTL design and verification experience from an APB-based SPI Master IP core.

I designed the core in Verilog HDL for processor-to-SPI peripheral communication, implementing the APB slave interface, baud-rate generator, shift register, slave-select logic, and top-level integration.

I developed functional testbenches and used Xilinx ISE to verify RTL behavior, control sequencing, data transfer, and SPI timing while debugging through simulation waveforms.

Through my VLSI Design and Verification internship at SR INNOVATIVE Technologies and ongoing training at Maven Silicon, I'm continuing to build practical skills in HDL-based design, simulation, verification, and industry-oriented VLSI workflows.