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Ritesh Jadhav

@riteshjadhav2

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RTL design engineer at Accenture who developed DMA, I3C, and SHA IPs and implemented I3C protocol features.

India

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At Accenture, I contributed to developing an IP from 0.1 implementation to 1.0 release, including RTL enhancements, feature additions, block integration, and design-quality checks.

I also assisted with SoC-level integration and developed Python scripts to automate feedthrough and pipeline insertion, mux-demux logic generation, and connectivity collateral generation.

At Cientra Tech Solutions Pvt. Ltd, I developed DMA architecture and RTL, and implemented an I3C Master Controller with Dynamic Address Assignment and Hot-Join features.

I also implemented SHA-1, SHA-256, SHA-384, and SHA-512 algorithms in RTL, and developed synthesis and LEC flows for SoC and multiple blocks.

Experience

Work history, roles, and key accomplishments

Current

Silicon Engineering Senior Analyst

Current

Accenture

Nov 2024 - Present (2 years)

Contributed to IP development from 0.1 to 1.0 release, delivering RTL enhancements and quality closure. Performed end-to-end design quality checks including Lint, CDC, RDC, Synthesis, and LEC, and assisted in SoC-level integration with Python-based automation scripts.

RTL Design Microarchitecture IP Development SOC Integration Linting CDC RDC Synthesis LEC Verilog SystemVerilog Python Perforce

RTL Design Engineer I

Cientra Tech Solutions Pvt. Ltd

Mar 2023 - Nov 2024 (1 year 8 months)

Developed synthesis and LEC flow setups for SoC and multiple blocks, and performed LEC checks across 13 macros/IPs. Developed DMA, I3C, and SHA IP architectures, implemented RTL, and set up quality flows including Lint, CDC, and Synthesis.

RTL Design Synthesis LEC Linting CDC DMA I3C SHA SystemVerilog Python Git Jira

Education

Degrees, certifications, and relevant coursework

MVP's KBT College of Engineering

Bachelor of Engineering, Electronics and Telecommunication Engineering

2019 - 2022

Bachelor of Engineering in Electronics and Telecommunication Engineering from MVP's KBT College of Engineering, Nashik, Maharashtra, from 2019 to 2022.