sayeekumar swaminathan

SS

Looking for a job

sayeekumar swaminathan

@sayeekumarswaminatha

I build and verify RTL processors, microarchitecture, and hardware test suites.

What I'm looking for

I'm seeking a real-time hardware engineering or verification role where I can build RTL, develop verification suites, diagnose synthesis and simulation discrepancies, and work on processor microarchitecture.

I've built RTL designs and verification suites for RISC-V and custom-ISA processors, including microcode control units, branch prediction, UART verification, and a pipelined 32-bit RISC-V processor.

At Phinity, I authored microarchitectural specifications and hardened AI training datasets through traceable automated testing, mutation testing, gate-level simulation analysis, and technical benchmark audits.

At Turing, I developed Verilog and SystemVerilog datapoints for NVIDIA's VerilogEval LLM, using Cocotb alongside Cadence Xcelium and Synopsys VCS.

I'm seeking a real-time hardware engineering or verification role where I can apply RTL design, simulation, synthesis, and evidence-driven verification skills.

Experience

Work history, roles, and key accomplishments

PH

RTL Training Data Engineer

Phinity

Nov 2025 - Sep 2026 (10 months)

Authored and hardened microarchitectural specifications for RTL subsystems and designed large-scale hidden verification suites for AI training data generation.

Verilog SystemVerilog RTL Design RTL Verification TestBench Development Gate Level Simulation Mutation Testing Cocotb Synopsys VCS Cadence Xcelium Python

TU

LLM Trainer

Turing

Oct 2024 - Sep 2025 (11 months)

Developed Verilog and SystemVerilog RTL and verification datapoints for training NVIDIA's VerilogEval LLM, using Cocotb and industrial simulators.

Verilog SystemVerilog RTL Design RTL Verification Cocotb Cadence Xcelium Synopsys VCS Python

CL

Senior Engineer

Cisma Consultants Pvt Limited

Feb 2022 - Jul 2024 (2 years 5 months)

Designed and verified RISC-V processor components and microcode control units using Verilog HDL and industry-standard tools.

Verilog RTL Design RTL Verification RISC V Synopsys VCS Cadence Xcelium Xilinx Vivado AWS FPGA OpenLane C Python

EL

Java Programmer

eG Innovations Pvt Ltd

Oct 2021 - Feb 2022 (4 months)

Developed Java modules for data collection and monitoring, and deployed applications on Tomcat Server.

Java Tomcat Servlet Application Monitoring

RC

Assistant Professor

R.M.D. Engineering College

May 2012 - Oct 2021 (9 years 5 months)

Taught microprocessor and microcontroller architecture courses for undergraduate Electrical and Electronics Engineering students.

Microprocessor Microcontroller Architecture Embedded Systems Digital Logic Teaching

Education

Degrees, certifications, and relevant coursework

VU

Vel Tech Dr. RR and Dr. SR Technical University

M.Tech, Embedded Systems Technology

2010 - 2012

Pursued M.Tech in Embedded Systems Technology from 2010 to 2012.

MC

M.N.M. Jain Engineering College

B.E., Electrical and Electronics Engineering

2006 - 2010

Completed B.E. in Electrical and Electronics Engineering from 2006 to 2010.

Tech stack

Software and tools used professionally

Bazel

Python

Java

C++

C

Linux

Meson

Availability

Looking for a job

Location

India

Authorized to work in

Salary expectations

200k+ USD

Job categories

RTL Design Engineer Verification Engineer Embedded Systems Engineer AI Training Data Specialist

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