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Pratibha Kalaichelvan

@pratibhakalaichelvan

Senior FPGA Engineer at AUTOTEC SYSTEM PVT. LIMITED, developing high-speed FPGA data pipelines for a DRDO defense project.

India

Message

What I'm looking for

I’m looking to use and enhance my FPGA design, synthesis, and verification skills in a company that encourages continuous education and employee development, in a dynamic environment where I can interact and work efficiently.

At AUTOTEC SYSTEM PVT. LIMITED, I engineer Verilog and VHDL logic for a DRDO high-performance FPGA board project. I designed data acquisition pipelines using LVDS, ADC/DAC interfaces, and DDR memory, and led board bring-up and hardware debugging.

At SAMEER-CEM, GOVT of India, I developed an AD9361 software-defined radio on the Xilinx Zynq PicoZed platform, implementing DDC, NCO, and decimating FIR filters in VHDL. As a Research Assistant at American University of RAS AL Khaimah, I implemented FPGA-based FFT processing for an RF sensor and integrated NB-IoT modules.

Experience

Work history, roles, and key accomplishments

Current

Senior FPGA Engineer

Current

Autotec System Pvt. Limited

Apr 2024 - Present (2 years 6 months)

Engineered complex multi-clock domain digital logic in Verilog and VHDL for real-time embedded defense systems. Led board bring-up, verification, and timing closure on Xilinx FPGAs.

Verilog VHDL Xilinx Vivado LVDS ADC DAC DDR JTAG Oscilloscopes Logic Analyzers SDC XDC Timing Closure Board Bring Up

Research Assistant

American University of Ras Al Khaimah

May 2020 - May 2022 (2 years)

Architected FPGA-based digital front-end for a custom RF sensor, implementing FFT algorithms and integrating with NB-IoT for wireless data transmission.

FPGA RTL Verilog VHDL FFT DSPs AD9082 SOC NB IoT Matlab Embedded Firmware

Research Scientist

SAMEER-CEM, Govt of India

Jun 2018 - May 2020 (1 year 11 months)

Developed a wideband SDR system on Xilinx Zynq PicoZed platform, configuring AD9361 RF transceiver and implementing DSP algorithms in VHDL. Achieved timing closure and validated with RF lab equipment.

SDR AD9361 Xilinx Zynq SoCs PicoZed VHDL LVDS AXI4 Stream DDC Programming NCO FIR Vivado STA RF Testing C SPI I2C UART GPIO

Education

Degrees, certifications, and relevant coursework

SASTRA University

M.Tech, VLSI Design

Grade: 8.47 CGPA

Pursued M.Tech in VLSI Design at SASTRA University, Tanjavur, Tamil Nadu, graduating in May 2018 with a CGPA of 8.47.

Shri Shankaracharya Group of Institutions

B.E., Electronics and Telecommunication

Grade: 8.02 CGPA

Completed B.E. in Electronics and Telecommunication from Shri Shankaracharya Group of Institutions, Bhilai, Chhattisgarh, in May 2015 with a CGPA of 8.02.