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Supam User

@supamuser

ECE student seeking a VLSI, RTL, or FPGA internship; implemented an FPGA-based FM modulator and ADPLL-based FM demodulator.

India

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What I'm looking for

I’m seeking a VLSI, RTL, or FPGA internship to apply my VHDL, digital design, simulation, and FPGA development skills while gaining practical exposure to semiconductor design workflows.

At NIT Jamshedpur, I designed and implemented digital communication and DSP architectures using VHDL and Xilinx Vivado. I developed an FPGA-based FM modulator and an ADPLL-based FM demodulator.

I converted MATLAB and Simulink algorithmic models into hardware-oriented RTL implementations. I also performed RTL simulation, synthesis, implementation, timing analysis, and FPGA validation on the Basys 3 platform.

For hardware-level signal validation and debugging, I used an oscilloscope and function generator. I’m seeking a VLSI, RTL, or FPGA internship where I can apply my digital design and FPGA development skills while gaining practical exposure to semiconductor design workflows.

Experience

Work history, roles, and key accomplishments

FPGA / VLSI Research Internship

NIT Jamshedpur

Designed and implemented digital communication and DSP architectures using VHDL and Xilinx Vivado. Developed an FPGA-based FM modulator and ADPLL-based FM demodulator, and performed RTL simulation, synthesis, implementation, timing analysis, and FPGA validation on the Basys 3 platform.

VHDL Xilinx Vivado FPGA RTL Design DSPs Matlab Simulink Static Timing Analysis Synthesis Implementation Basys 3 Oscilloscopes Function Generators

Education

Degrees, certifications, and relevant coursework

Jalpaiguri Government Engineering College

B.Tech., Electronics and Communication Engineering

2024 -

Grade: 8.95

Pursuing B.Tech. in Electronics and Communication Engineering with a CGPA of 8.95. Coursework includes Digital Electronics, Microprocessors & Microcontrollers, Computer Architecture and Organization, Signal & System, and Communication System.