Aditya Shekhawat

I build RTL in Verilog HDL and SystemVerilog for combinational and sequential digital logic, from FSM design to testbench-driven functional verification. I write test cases, run simulations in ModelSim and Xilinx Vivado, and debug using waveforms.

At CSIR-CEERI, I worked on system-level modeling and control strategies for a resonant Dual Active Bridge (DAB) topology for an on-board EV charger across multiple operating modes. I also wrote and executed 15+ test cases to validate design performance.

On the processor side, I’ve designed a tiny GPU-inspired SIMD processor in Verilog HDL in Vivado, including a 3-stage pipelined core with a SIMD ALU lane array and an FSM-based control unit. I validated its behavior through RTL-level functional verification.

I also prototype and verify hardware security and low-power oriented RTL, including FPGA debugging and simulation runs for countermeasures. My workflow includes STA, setup & hold analysis, and logic synthesis/timing closure concepts with tools like Synopsys Design Compiler.