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Pragati Piragannavar

@pragatipiragannavar

ASIC and SoC design verification engineer who verified an AXI4-Lite slave and built RTL projects including a RISC-V RV32I processor.

India

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What I'm looking for

I’m looking to join a dynamic team of professionals as an ASIC and SoC Design Engineer, where I can share my expertise and contribute to the organization’s success.

At Igeek Technologies, I developed and verified an AXI4-Lite slave module with 256x32-bit internal memory, read/write operations, AXI handshake logic, and address decoding. I used a custom SystemVerilog testbench with protocol-compliant stimulus and coverage analysis.

My projects include RTL design and verification for a RISC-V RV32I processor, a full-duplex UART system, an AXI4-Lite-to-APB bridge, and a configurable 1x3 router. I’m pursuing a Post Graduate Program in VLSI ASIC RTL / SoC Design and Verification at M S Ramaiah Institute of Technology.

Experience

Work history, roles, and key accomplishments

Project Intern

Igeek Technologies

Sep 2023 - Oct 2023 (1 month)

Developed an AXI4-Lite slave interface with RTL design and verification using Verilog and SystemVerilog. Implemented AXI handshake logic, address decoding, and verified with a custom testbench and coverage analysis.

Verilog SystemVerilog AXI4 Lite QuestaSim RTL Design Verification Coverage Analysis