Open to opportunities

Neshitha Nichanametla

@neshithanichanametla

Message

I build Verilog RISC-V processors and SoC subsystems through RTL-to-GDSII VLSI flows.

India

Message

What I'm looking for

I'm looking for opportunities in VLSI, RTL, digital design, RISC-V, and semiconductor technologies where I can contribute across the RTL-to-GDSII flow and continue building practical design skills.

I've designed a 32-bit single-cycle RISC-V processor in Verilog HDL, implementing RV32I arithmetic, logical, memory-access, and control-flow instructions and verifying it with RISC-V test programs.

For a RISC-V-based SoC subsystem, I used the PicoRV32 core and AXI4-Lite peripherals, then ran synthesis in Yosys and the complete physical-design flow in OpenLane/OpenROAD. I performed static timing analysis with OpenSTA, verified layouts in Magic VLSI and KLayout, and generated a final GDSII layout while analyzing power, performance, and area.

I'm a final-year Integrated B.Tech + M.Tech Electronics and Communication Engineering student at JNTUH, focused on VLSI, RTL, digital system design, RISC-V architecture, and semiconductor technologies.

Experience

Work history, roles, and key accomplishments

RISC-V Processor Designer

Self Employed

Designed and implemented a 32-bit RISC-V processor using single-cycle architecture, including a subset of the RV32I ISA. Developed the processor in Verilog HDL and verified functionality through simulation.

Verilog RTL Design RISC V Simulation TestBench Development