Open to opportunities

SHAKKTHI NARESH User

@shakkthinareshuser

Message

I build semiconductor device simulations and lightweight wafer-defect ML models.

India

Message

What I'm looking for

I'm looking to apply my semiconductor device knowledge and practical programming skills to device development, test methodologies, data-driven wafer analysis, yield improvement, or software-adjacent engineering roles.

I've built a 2.65 MB FCN-SVM wafer-map defect classification model that achieved 90% accuracy, handling preprocessing, feature extraction, training, evaluation, and deployment optimization in Python, TensorFlow, NumPy, and Pandas.

Through my MTech in VLSI Design and an exchange program at Asia University, I developed hands-on experience in semiconductor fabrication concepts, cleanroom metrology, TCAD simulation, and digital design. I also simulated and optimized double-gated tunnel FETs in Synopsys Sentaurus, analyzing HfO₂ scaling, tunneling behavior, meshing strategies, and electrical characteristics.

Experience

Work history, roles, and key accomplishments

Current

AR Assosiate

Current

Omega Healthcare Management Services

Jan 2026 - Present (8 months)

Out-bound voice process worker responsible for obtaining prior-authorization for insurance

Education

Degrees, certifications, and relevant coursework

Sastra Deemed University

Master of Technology, VLSI Design

2024 - 2025

Grade: 8.11/10

Activities and societies: Exchange program at Asia University, Taichung, Taiwan (2024–2025); exposure to semiconductor fabrication and cleanroom metrology at TSRI.

MTech in VLSI Design with a CGPA of 8.11/10. Participated in a second-year exchange program at Asia University, Taichung, Taiwan, and gained exposure to semiconductor fabrication concepts and cleanroom metrology at Taiwan Semiconductor Research Institute (TSRI).